1. Field of Invention
Apparatuses consistent with the present invention relate to semiconductor packages and methods for manufacturing semiconductor packages. More particularly, the present invention relates to flip-chip leadframe semiconductor packages designed to improve mold flow around the leadframe and semiconductor die.
2. Description of the Related Art
Leadframe semiconductor packages uses metal leads that extend outside the package housing. FIG. 1 is an example of a conventional leadframe package. The package 1 includes a semiconductor die 2 attached to a substrate 3 with an adhesive 4. Wire bonds 5 provide internal electrical connections to the substrate 3 and external connections to the leadframe 6. An encapsulant 7 covers the semiconductor die 2, substrate 3, wire bonds 5 and portions of the leadframe 6.
Another type of semiconductor package incorporates leadframe and “flip chip” technology. FIGS. 2 and 3 show examples of leadframe semiconductor packages that use flip chip technology instead of wire bonding technology. The flip chip process is a method for interconnecting semiconductor dies to external circuitry with solder bumps that have been deposited onto the chip pads. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry (e.g., a circuit board or another chip or wafer), it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is flowed to complete the interconnect.
In FIGS. 2 and 3, the flip chip lead frame packages 8, 9 include a semiconductor die 2 attached to a leadframe 10 by conductive solder bumps or balls 11. An encapsulant 7 covers the semiconductor die 2 and portions of the leadframe 6.
FIGS. 4A through 4F show an embodiment of manufacturing a flip chip leadframe semiconductor package. First, in FIG. 4A, the semiconductor die 2 is attached to the leadframe 10 by solder bumps 11. Next, the semiconductor die and leadframe are placed in a mold (not shown) and an encapsulant is injected into the mold. FIGS. 4B though 4D show how the encapsulant (shown in black) flows in the mold.
During the initial flow (FIG. 4B) the encapsulant is injected into a mold gate or mold inlet (not shown) and the encapsulant flow is balanced. However, as shown in FIG. 4C, as the encapsulant flows in the area of the semiconductor die, the flow becomes significantly unbalanced. The encapsulant flows faster in the bottom channel, which is wider, than in the top channel, which is narrower. As a result, as shown in FIG. 4D, the encapsulant flows completely through the bottom channel and begins to turn up to the top channel. When the flow from the bottom channel meets the flow from the top channel, an air bubble 12 can be formed. A tiny air vent 22 is typically located at the end of the package where the flows are expected to meet. Air vent 22 is supposed to allow the air bubble 15 that is formed at the end of the package to be vented from the package. However, because of the uneven flows, the air bubble 15 does not meet at the air vent 22. As shown in FIG. 4E, this air bubble, can create a void or incomplete fill 13 after the molding is completed. This is in contrast to a package with a good mold result which is shown in FIG. 4F.
A void or incomplete fill is a defect which is undesirable in semiconductor packages because it can cause a weak point in the molding compound. There are varying sizes of this defect, some that are detectable by the naked eye and others that are in the range of a micrometer in diameter. Moisture can penetrate through this weak point of the compound and then settle in the defect. When the package goes through the reflow process, the moisture which is trapped in the compound changes to a gas and expands, which causes a popcorn effect and then delamination. Delamination is common problem for semiconductor packages. In additional, if the defect occurs on the surface of the package, it is also considered to be a mold visual defect. In some cases, this external defect can make the identification information that is stamped on the device illegible.
Therefore, these is a need for a new design/method that will enable the production of flip chip leadframe semiconductor packages to be produced that will not have voids/incomplete fills in the encapsulant.